[jeremyb]

DDR Enablement Command:

Cmd 0x5C 0xC5 0x55
Addr 0x00
Data 0x01
 
Cmd 0x55
Addr 0x20
Data 0x1

Register 0x20
Value 0x00 = Disable
Value 0x01 = Enable

When DDR is Enabled the chip id changes to
45 3c 9b b3 7e f1

As stated by Arvika, this chip comes in different models/configs..

Chip Config:

// Chip
Company Toshiba
Name Monolith
ID code 98 3c 98 b3
 
// Structure
Bus 8
Banks 1 x 32 GB
Page 18336
Block 0xa12800
Blocks 0xf68
 
// Read
Cmd WL
Col 2
Row 3
DDR false
 
// Timings
RE_Up 2
RE_Down 2
 
// Special
Power
Retry
Skip_Mask_1 0xff
Skip_Page_1 0xc0
Skip_Mask_2 0xffffffff
Skip_Page_2 0xffffffff
Join CE

This chip uses Registers 0x21 0x22 and 0x24 for Read Retry, use plot to find the ideal values.

Read Retry address space is 64 values.

Register 0x21
Not sure what to make of it, it seems like it adjusts the overall sensitivity, some uncorrectable areas are corrected at the expensive of making good areas red. There is no curve Use ECC Combine..

[jeremyb]

SanDisk v2 has been implemented in Flash Extractor for this generation of NAND chip. The address space is 64 (0x40) so you don't need to scan the entire range with tune or plot. Also because the address space is so narrow its difficult to read with plot.

Reg 2 is the major register, 1, and 0 are minor.

The easier method to solve Read Retry is below.

1. Find the Layout
2. Launch Read Retry mode
3. Under Properties

Retry = Sandisk v2 / 00 00 00
Ignore Busy = True

4. Under Tune

Regs = 2,1,0
Delta = 32
Repeat = 1

and let it run

[Сергей]

Sandisk v2 is not ready, i think

I need some more chips to test it

Some combinations of register values change non-DDR to DDR

So need adjust registers

[jeremyb]

[jeremyb]

Here's a video showing it work....

https://youtu.be/5bxg5O4EdcU

[pcimage]

Works a treat Jeremy, thanks!